EDN

Xilinx Improves Design Flow for Industry’s Only Proven Partial Reconfiguration FPGA Technology with ISE Design Suite 12.2

SAN JOSE, Calif., July 27 /PRNewswire/ –Xilinx, Inc. (Nasdaq: XLNX) today announced the availability of its fourth generation partial reconfiguration design flow and new improvements to its ...
mccormick.northwestern.edu

COMP_ENG 355: ASIC and FPGA Design

This course will introduce students to practical design methodologies for developing applications for FPGAs and ASICs. You will learn the fundamentals for FPGA and ASIC design through software coding ...
Design-Reuse

Automatic C-to-VHDL testbench generation shortens FPGA development time

Verifying behavior early and often has become critical with FPGAs. Newer generations of FPGAs have gate counts that rival the largest custom ASICs of five years ago. This fact, coupled with the broad ...
TechRepublic

Design and Implementation of I2c Master Controller on FPGA using VHDL

In this paper, the authors proposed on I2c protocol following master controller. This controller is connected to a microprocessor or computer and reads 8 bit instructions following I2C protocol. The ...
Semiconductor Engineering

Challenges In Using HLS For FPGA Design

High-level synthesis (HLS) tools, which transform C/C++ source code to Verilog/VHDL, have been commercially available for over 15 years. HLS tools from FPGA vendors and EDA companies promise improved ...
Electronic Design

Mentor Graphics, Mathworks Optimize FPGA Design Flow

Mentor Graphics has upgraded its Precision Synthesis tool to include hardware description language (HDL) generated by MathWorks Simulink HDL Coder. Mentor Graphics has upgraded its Precision Synthesis ...
Design-Reuse

From Behavioral to RTL Design Flow in SystemC

This paper reports the scientific collaboration between LLR and PROSILOG. The aim of this collaboration was to show the possibility to quickly implement a system into a FPGA, using SystemC 4 as the ...
EDN

Demonstrating ASIC IP performance and quality demands an FPGA-neutral design flow

Companies designing new system-on-chip (SoC) products are subject to ongoing market pressure to do more with less and achieve higher returns. The result is shrinking engineering teams, reduced design ...
TechRepublic

Design of FPGA Based 32-Bit Floating Point Arithmetic Unit and Verification of Its VHDL Code Using MATLAB

Most of the algorithms implemented in FPGAs used to be fixed-point. Floating-point operations are useful for computations involving large dynamic range, but they require significantly more resources ...
Electronics Weekly

Xilinx aims to widen FPGA use in HDTV designs

Xilinx is looking to get Spartan-6 FPGAs designed into high definition digital TV systems. At last week’s CES in Las Vegas, the company introduced its first design platform aimed specifically at ...
Hackaday

Apple II FPGA

[Stephen Edwards] had some time one Christmas. So he took a DE2 FPGA board and using VHDL built a pretty faithful reproduction of an Apple II+ computer. He took advantage of VHDL modules for the 6502 ...