However, the very definition of a transition fault model creates the opportunity to actually miss the detection of open defects inside of standard cells. This was recently proved in production ...

Modern semiconductor testing is based on the notion of a fault model, that is, the expected behavior (response) of a circuit when a defect is present. ATPG (automatic test pattern generation) tools ...

Stuck-at and transition fault models describe very basic defect effects. Stuck-at faults model both stuck at a logic-0 state (stuck-at-0) and stuck at a logic-1 state (stuck-at-1).

This white paper describes the functionality of user defined fault models (UDFM), including gate exhaustive UDFM and cell-aware UDFM, and the effectiveness of lowering DPM in devices. To achieve today ...

Two popular methods to generate test patterns for scan-based testing are the launch-from-capture technique (broadside delay test) and the launch-from-shift technique (skewed load d elay test).

An effective gate-exhaustive fault model would need to consider a third don’t-care state applied to inputs. Thus, an eight-input logic model could require as many as 3 8, or 6561 patterns.

University of California - Berkeley image: Gregory McLaskey (L) and Steven Glaser examine a tabletop model of a fault at UC Berkeley. view more ...

ATPG efficiency is another important consideration that is influenced by the fault model under consideration, the type of circuit under test (full scan, synchronous sequential, or asynchronous ...