Modern semiconductor testing is based on the notion of a fault model, that is, the expected behavior (response) of a circuit when a defect is present. ATPG (automatic test pattern generation) tools ...

The adoption of this new fault model enables us to detect all possible hold time violations effectively and also makes diagnosis quickly and easily. The following figure is a representation of hold ...

ATPG efficiency is another important consideration that is influenced by the fault model under consideration, the type of circuit under test (full scan, synchronous sequential, or asynchronous ...

Two popular methods to generate test patterns for scan-based testing are the launch-from-capture technique (broadside delay test) and the launch-from-shift technique (skewed load d elay test).

University of California - Berkeley image: Gregory McLaskey (L) and Steven Glaser examine a tabletop model of a fault at UC Berkeley. view more ...