EDN

Lattice Updates CPLD Design Tools

Lattice Semiconductor Corp. wants to make sure that, in the rush of attention to high-end FPGAs, the simpler CPLD programmable logic device is not forgotten. Version 1.4 of the ispLEVER Classic design ...
Design-Reuse

Lattice Announces Improved Synthesis and Power Optimization in CPLD Design Tools

HILLSBORO, OR, Aug 16, 2010 -- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of Version 1.4 of its ispLEVER(R) Classic design tool suite. The ispLEVER ...
Design-Reuse

Lattice Announces Updated, More Accessible CPLD Design Tools

ispLEVER Classic Version 1.3 Design Tools Feature Updated CPLD Support and Faster, Modular Installation HILLSBORO, OR - AUGUST 3, 2009 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today ...
EDN

Lattice upgrades wide logic-block CPLD family

SAN MATEO, Calif. — With the help of a process technology shift and some minor architectural changes, Lattice Semiconductor Corp. has raised the speed bar on its complex programmable logic device ...
Electronics Weekly

Lattice CPLD bridges gap between interfaces and bus architectures

A CPLD with on-chip phase locked loops, high speed I/O and extra wide logic functions has been introduced by Lattice. The ispMACH5000VG is aimed at bridging between communications interfaces and ...
Electronics Weekly

Lattice CPLD design tool supports discontinued devices

Lattice Semiconductor has announced version 1.3 of its ispLEVER Classic design tool suite which includes updated support for its CPLDs, including the ispMACH 4000 device family. The ispLEVER Classic 1 ...
Embedded

Leveraging FPGA and CPLD digital logic to implement analog to digital converters

Designers of digital systems are familiar with implementing the 'leftovers' of their digital design by using FPGAs and CPLDs to glue together various processors, memories, and standard function ...