EDN

Altera unveils Quartus II software version 8.1

The folks at Altera have unveiled their Quartus II software version 8.1 for CPLD, FPGA, and HardCopy ASIC designs. Based on internal benchmarks, the folks at Altera claim high-density FPGA compile ...
Design-Reuse

Altera verilog tutorial IP Listing

The BAY9 Virtual RF (VRF) is an IP core written in Verilog, that allows to emulate most system aspects of a typical RF transmission. When connected to a physical layer (PHY) core, the VRF IP ... The T ...
Design-Reuse

Altera Demonstrates its Comprehensive FPGA, SoC and Power Solutions at APEC 2015 Offering Greater Efficiencies in Electronic Design

Attend an Altera tutorial session, “FPGA Digital Control with MATLAB/Simulink and Altera DSP Builder” on Sunday, March 15, 2015 from 10:00 to 1:30 that will show attendees how a Field Programmable ...